Advanced FPGA Design
Architecture, Implementation, and Optimization
Chapter One
Architecting Speed
Sophisticated tool optimizations are often not good enough to meet most design
constraints if an arbitrary coding style is used. This chapter discusses the first of
three primary physical characteristics of a digital design: speed. This chapter also
discusses methods for architectural optimization in an FPGA.
There are three primary definitions of speed depending on the context of the
problem: throughput, latency, and timing. In the context of processing data in an
FPGA, throughput refers to the amount of data that is processed per clock cycle.
A common metric for throughput is bits per second. Latency refers to the time
between data input and processed data output. The typical metric for latency will
be time or clock cycles. Timing refers to the logic delays between sequential
elements. When we say a design does not "meet timing," we mean that the delay
of the critical path, that is, the largest delay between flip-flops (composed of
combinatorial delay, clk-to-out delay ... read full excerpt from Advanced FPGA Design: Architecture, Implementation, and Optimization ebook
