Nano-CMOS Circuit and Physical Design
Chapter One
NANO-CMOS SCALING PROBLEMS
AND IMPLICATIONS
1.1 DESIGN METHODOLOGY IN THE NANO-CMOS ERA
As process technology scales beyond 100-nm feature sizes, for functional and
high-yielding silicon the traditional design approach needs to be modified to
cope with the increased process variation, interconnect processing difficulties, and
other newly exacerbated physical effects. The scaling of gate oxide (Figure 1.1)
in the nano-CMOS regime results in a significant increase in gate direct tunneling
current. Subthreshold leakage and gate direct tunneling current (Figure 1.2)
are no longer second-order effects. The effect of gate-induced drain leakage
(GIDL) will be felt in designs, such as DRAM (Chapter 7) and low-power
SRAM (Chapter 9), where the gate voltage is driven negative with respect to the
source. If these effects are not taken care of, ... read full excerpt from Nano-CMOS Circuit and Physical Design ebook
